M-986-2A1PL【PDF 9/13 页】IC TRANSCEIVER MF 2CHAN 44-PLCC

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Sheet目录2007

5页 6页 7页 8页 [9页]10页 11页 12页 13页

M-986-2A1

www.clare.com

Rev. 3

Signal Description

Signal

Pin

I/O/Z

Description

D15-D8

18-11

I/O/Z

Unused. Leave open.

D7-D0

19-26

I/O/Z

8-bit coprocessor latch.

TBLF

Transmit buffer latch full flag.

RBLE

Receive buffer latch empty flag.

HI/LO

Latch byte select pin. Tie low.

BIO

Unused. Leave open.

I/O

Used by the external processor to read from the coprocessor latch by driving the

RD line active (low), thus enabling the output latch to drive the latched data.

When the data has been read, the external device must bring the RD line high.

EXINT

Unused. Leave open.

Microcomputer mode select pin. Tie low.

MC/PM

Coprocessor mode select pin. Tie low.

Reset input for initializing the device. When an active low is placed on RS pin for

a minimum of five clock cycles, RD and WR are forced high, and the data bus

(LD7 through LD0) goes to a high impedance state. The serial port clock and

transmit outputs also go to the high impedance state.

I/O

Used by the external processor to write data to the coprocessor port. To write

data the external processor drives the WR line low, places data on the data bus,

and then drives the WR line high to clock the data into the on-chip latch.

Watchdog signal. Toggles at least once every 10 milliseconds when the

processor is functioning properly. If the pin is not toggled at least once every 10

ms, the processor is lost and should be reset.

CLKOUT

System clock output (one-fourth crystal/CLKIN frequency, nominally 5.12 MHz).

Ground pin.

5V supply pin.

Crystal output pin for internal oscillator. If the internal oscillator is not used, this

pin should be left unconnected.

X2/CLKIN

Input pin to the internal oscillator (X2) from the crystal. Alternatively, an input pin

for the external oscillator (CLKIN).

DR1 & DR0

33 & 29

Serial-port receive-channel inputs. 2.048 MHz serial data is received in the receive

registers via these pins. DR0 = channel 1; DR1 = channel 2.

8 kHz internal serial-port framing output. If internal clocking is selected,

serial-port transmit and receive operations occur simultaneously on an active

(high) FR framing pulse.

DX1 & DX0

36 & 35

Serial-port transmit-channel outputs. 2.048 MHz serial data is transmitted from

the transmit registers on these pins. These outputs are in the high-impedance

state when not transmitting. DX0 = channel 1; DX1 = channel 2.

FSR

8 kHz external serial-port receive-framing input. If external clocking is selected,

data is received via the receive pins (DR1 and DR0) on the active (low) FSR input.

The falling edge of FSR initiates the receive process, and the rising edge causes

the M-986 to process the data.

SCLK

I/O/Z

2.048 MHz serial-port clock. Master clock for transmitting and receiving serial-

port data. Configured as an input in external clocking mode or output in internal

clocking mode. Reset (RS) forces SCLK to the high-impedance state.

FSX

8 kHz external serial-port transmit-framing input. If external clocking is enabled,

data is transmitted on the transmit pins (DX1, DX0) on the active (low) input. The

falling edge of FSX initiates the transmit process, and the rising edge causes the

M-986 to internally load data for the next cycle.

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